The present invention relates to a semiconductor device manufacturing method.
Various studies have been conducted on the manufacture of interlayer insulating film for covering wiring in order, for instance, to increase the degree of integration of a semiconductor device. Technologies concerning the manufacture of interlayer insulating film are described, for instance, in Japanese Patent Application Publications No. Hei 11 (1999)-40669, Hei 11 (1999)-176936, Hei 8 (1996)-255791, and 2000-91431. The technology described in Japanese Patent Application Publication No. Hei 11 (1999)-40669 forms an upper insulating film layer, which includes an insulating film etching component, over a lower insulating film layer. The technology described in Japanese Patent Application Publication No. Hei 11 (1999)-176936 forms an insulating film, etches the insulating film, and then forms another insulating film. Japanese Unexamined Patent Application Publications No. Hei 11 (1999)-40669 and Hei 11 (1999)-176936 state that wiring formed over a semiconductor substrate prevents a void from being generated in the interlayer insulating film.
The technology described in Japanese Patent Application Publication No. Hei 8 (1996)-255791 forms a BPSG film over a silicon substrate, over which a titanium silicide film is formed, via an oxide silicon film. The publication states that the technology can suppress an increase in the resistance value of the titanium silicide film. The technology described in Japanese Patent Application Publication No. 2000-91431 forms a BPSG film or other similar interlayer insulating film over a silicon substrate and then forms a plasma TEOS film or other similar interlayer insulating film made of a harder material. The publication states that the technology can form a sufficiently planar interlayer insulating film.